In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative to the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (“SDRAMs”), synchronous static random access memories (“SSRAMs”), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device are typically synchronized to external operations. For example, data is read from the memory device in synchronism with the external clock signal. To provide the data at the proper times, an internal clock signal is developed in response to the external clock signal, and is typically applied to latches contained in the memory device to clock the data into the latches. The internal clock signal and external clock must be synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully provide the data. In the present description, “external” refers to signals and operations outside of the memory device, and “internal” refers to signals and operations within the memory device. Moreover, although the present description is directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.
Internal circuitry in the memory device that generates the internal clock signal necessarily introduces some time delay, causing the internal clock signal to be phase shifted relative to the external clock signal. As long as the phase-shift is minimal, timing within the memory device can be easily synchronized to the external timing. As used herein, the term synchronized includes signals that are coincident and signals that have a desired delay relative to one another. However, with higher frequency clock signals, the time delay introduced by the internal circuitry becomes more significant. This is true because as the frequency of the external clock signal increases, the period of the signal decreases and thus even small delays introduced by the internal circuitry correspond to significant phase shifts between the internal and external clock signals. As a result of intrinsic delays, the data provided by the memory device may not be valid at the time the internal clock signal clocks the latches.
Additionally, as the frequency of the external clock increases, variations in the duty cycle of the clock signal introduce a greater duty cycle error. An ideal duty cycle for a clock signal is typically 50 percent. That is, over the period of a clock cycle, the clock signal is HIGH for 50 percent of the period. As the period of the clock signals become shorter due to the increased clock frequency, a clock variation that results in a subtle shift in duty cycle, and which can be ignored at a lower clock frequency, may result in a much more significant shift in the duty cycle of the higher frequency clock signal. In such instances, if the duty cycle of the clock signal is left uncorrected, timing errors may cause the memory device to fail.
To synchronize external and internal clock signals in modern synchronous memory devices, a number of different approaches have been considered and utilized, including delay-locked loops (“DLLs”) with duty cycle correction (“DCC”) circuits. Clock synchronizing circuits, such as DLLs, generate output clock signals that are in phase, or synchronized, with input clock signals. A DCC circuit can correct a distorted duty cycle of clock signals. One DCC technique takes a first clock signal and a second clock signal that is 180 degrees out of phase from the first clock signal and shifts the phase of one of the two clock signals so that rising edges of the first and second clock signals correspond to rising edges of two clock signals having ideal 50 percent duty cycles. Although the clock signals still appear distorted, circuitry operating in response to rising edges of the first and second clock signals will function as if provided with clock signals having 50 percent duty cycles.
FIG. 1 illustrates a DLL 100. The DLL 100 operates in a conventional manner, with it providing delayed output clock signals DCLK0 and DCLK180 that are in phase with input clock signals CLK0 and CLK180, respectively. The CLK0 and CLK180 signals are 180 degrees out-of-phase, as are the DCLK0 and DCLK180 signals. Operation of the DLL 100 will be described ignoring operation of the tAC trim and tOH trim circuits 140, 150, the operation of which will be described in detail below. The CLK0 and CLK180 signals are buffered by input buffer circuits 102, 104 and provided to a variable delay line 106. The variable delay line 106 delays the CLK0 and CLK180 signals by a delay controlled by a phase detector 110. The delayed CLK0 and CLK180 signals are buffered by output clock buffer circuit 112, 114. The delayed CLK0 signal output by the variable delay line 106 is further delayed by a model delay 108 having a delay equal to the total intrinsic delay of the input and output buffer circuits 102, 104 and 112, 114. The phase detector 110 receives and compares the phase of the buffered CLK0 signal and a CLKFB signal output by the model delay 108. Based on the phase of the two signals, the variable delay line 106 is adjusted until the buffered CLK0 signal and the CLKFB signal are in phase. Under this condition, the DLL is described as being “locked” and the resulting DCLK0 and DCLK180 signals will be in phase (i.e., “synchronized”) with the CLK0 and CLK180 signals.
The variable delay line 106 has a range of adjustable delay between a minimum delay and a maximum adjustable delay. In order to accommodate a wide range of input clock frequencies and variations in circuit performance that can result from manufacturing variations, it is desirable for the variable delay line 106 to have a wide range of adjustable delay. Providing such an adjustable delay circuit, however, requires a considerable number of delay stages. This results in a relatively “large” circuit that consumes significant power. Additionally, typical delay stages include delay circuits having respective delays that are affected by electrical noise, such as power noise. As a result, an input clock signal that propagates through a long chain of delay stages is more susceptible to “clock jitter” since the delay of each stage is affected by electrical noise and the total noise-induced shift in delay is additive over the entire length of delay stages. Thus, the range of adjustable delay that an adjustable delay is designed to provide is a compromise between providing sufficient delay to accommodate an acceptable range of clock and account for variations in circuit performance, and the desire to reduce circuit size, power consumption and susceptibility to noise-induced clock jitter.
With the range of adjustable delay of the variable delay line 106 tailored to balance competing considerations, it may be necessary to trim a static or non-adjusted delay of the DLL 100 due to a mismatch between the model delay 108 and the actual delay of the input buffer circuits 102, 104 and the output clock buffer circuits 112, 114. The static delay of the DLL 100 for tAC is generally represented by the variable delay line 106, but set to a default delay, and the model delay 108. The static delay of the DLL 100 for tOH is generally represented by the default delay of the variable delay line. The tAC and tOH trim circuits 140, 150 provide examples of this trimming functionality. The tAC trim circuit 140 is used to trim static clock synchronization accuracy and the tOH trim circuit 150 is used to trim static duty cycle. The tAC trim circuit 140 includes a static delay circuit 120 that provides a fixed delay and further includes an adjustable delay 122 having a delay that is adjusted by a trim decoder circuit 124. The trim decoder circuit 124 receives a tAC trim signal that is used to set the amount of delay trim for the tAC trim circuit 140. The tOH trim circuit 150 similarly includes a static delay circuit 130 and an adjustable delay circuit 132 that has a delay that can be adjusted by a tOH trim decoder 134. A tOH trim signal is used to set the desired delay trim of the tOH trim circuit 150. The tAC and tOH trim signals are typically determined during testing of the memory device where its performance is measured and compared to performance specifications. Where the memory device is not performing to tAC and tOH specifications, trim signals suitable to correct the deviations are generated and applied accordingly.
FIG. 2 illustrates the static delay 120, 130 and the adjustable delay 122, 132 of the tAC and tOH trim circuits 140, 150. In the case of the tAC trim circuit, the CLK0 and CLKFB signals are provided to the static delay 120 and the adjustable delay 122 to produce the delayed output signals CLK0_trim and CLKFB_trim signals, all respectively. As for the tOH trim circuit, CLK0VD and CLK180VD output by the variable delay 106 are further delayed by the static delay 130 and the adjustable delay 132 to provide CLK0VD_trim and CLK180VD_trim signals, all respectively. The adjustable delay 122, 132 provides a range of adjustable delay between a minimum delay, typically an intrinsic delay 204 and a maximum delay. The tAC/tOH trim decoder 124, 134 adjusts the delay of the adjustable delay 122, 132 according to a respective trim signal. The default delay of the adjustable delay 122, 132 is typically one-half of the maximum delay. The static delay circuit 120, 130 has an intrinsic delay 202 and also provides a fixed delay that is approximately one-half of the maximum delay of the adjustable delay 122, 132.
By providing a static delay circuit 120, 130 of one-half of the maximum delay and an adjustable delay 122, 132, the phase of a first clock signal can be shifted in time in either the positive or negative direction relative to the phase of a second clock signal. That is, the first clock signal and be shifted earlier or later in time relative to the second clock signal. For example, with particular reference to the CLK0 and CLKFB signals, assume that in an initial condition the CLK0 and CLKFB signals are in phase and the adjustable delay 122 is set to provide the same delay as the static delay circuit 120 (i.e., one-half the maximum adjustable delay). The CLKFB_trim signal can be shifted earlier in time relative to the CLK0_trim signal by adjusting the adjustable delay 122 to provide less delay than the static delay circuit 120 (i.e., less than one-half the maximum adjustable delay). Conversely, the CLKFB_trim signal can be shifted later in time relative to the CLK0_trim signal by adjusting the adjustable delay 122 to provide more delay than the static delay circuit 120 (i.e., more than one-half the maximum adjustable delay). Shifting the CLKFB_trim signal relative to the CLK0_trim signal can be used to trim tAC since the phase detector 110 (FIG. 1) will adjust the variable delay line 106 according to the phase relationship of the CLK0_trim and CLKFB_trim signals. Where the tAC specifications are not met, the CLKFB_trim signal can be shifted either earlier or later in time relative to the CLK0_trim signal so that the synchronization of the CLK0_trim and CLKFB_trim signals by the variable delay line 106 is possible. As previously discussed, such a situation can occur due to variations in the fabrication process of the memory device or due to timing differences between the real clock path and that of the clock path including the model delay 108.
The tOH trim circuit 150 operates in a manner similar to the tAC trim circuit. A DCC circuit (not shown) can precisely adjust the phases of the DCLK0 and DCLK180 signals to provide rising clock edges corresponding to an ideal 50% duty cycle. However, the DCLK0 and DCLK180 signals should be in a correctible range of the DCC circuit. The tOH trim circuit 150 can be used to adjust the phases of the DCLK0 and DCLK180 signals so that a distorted duty cycle outside of the correctible range can be corrected by the DCC. The tOH trim circuit can shift the phase of the CLK180VD_trim signal to an earlier or later time relative to the CLKVD0_trim signal. For a duty cycle that is too low for correction by the DCC circuit, the adjustable delay 132 can be set to provide more delay than the static delay circuit 130 in order to “increase” the duty cycle so that it can be corrected. For a duty cycle that is too high for correction by the DCC circuit, the adjustable delay 132 can be set to provide less delay than the static delay circuit 130 in order to “decrease” the duty cycle so that it can be corrected.
Although the tAC and tOH trim circuits 140, 150 can provide adjustability for trimming tAC and tOH, the static delay circuit 120, 130 necessarily adds a delay of one-half the maximum adjustable delay of the adjustable delay 122 to the CLK0 and CLK0VD signals, even if tAC and tOH trimming is unnecessary. In the cases where tAC and tOH trimming are required, the delay of the adjustable delay 122, 132 will typically be centered around the default setting of one-half of its maximum adjustable delay. Thus, in either case, both the CLK0, CLKFB and CLK0VD, CLK180VD signals will necessarily be delayed. As previously discussed, adding delay increases susceptibility to noise-induced jitter and also presents the possibility of increased power consumption. In applications where having precision clock signals and relatively low power consumption are both desirable, the costs associated with conventional delay trimming circuits may be unacceptable.
Therefore, there is a need for a delay trimming circuit that can trim delays using less forward delay, and as a result, is less susceptible to noise-induced clock jitter and has lower power consumption.